The present invention generally relates to the field of semiconductor processing, and more particularly relates to optimizing post exposure bake processes for semiconductor device fabrication.
Lithography, in the context of building integrated circuits (ICs) such as microprocessors and memory chips, is a highly specialized printing process used to put detailed patterns onto silicon wafers. An image containing the desired pattern is projected onto the wafer through a mask defining the pattern. Prior to light projection through the mask, the wafer is coated with a thin layer of photosensitive material called “resist”. The resist material may then be pre-baked to drive-off excess solvent. After the pre-baking process, the wafer is exposed to one or more patterns of light. For positive-tone photoresists, the bright parts of the image pattern cause chemical reactions that result in the resist material becoming more soluble, and thus dissolve away in a developer liquid; the dark portions of the image remaining insoluble. For negative-tone resists, the exposed (bright image parts) photoresist remains after development.
A post exposure bake (PEB) is then performed to help reduce standing wave effects caused by the destructive/constructive interference patterns of the incident light during the exposure process. The PEB process may also thermally catalyze chemical reactions and increase resolution and line width. Once the PEB process has completed, a development process is performed where the desired portions of the resist material are removed. A baking process may then be performed to solidify the remaining resist material. After development, the resist forms a stenciled pattern across the wafer surface which accurately matches the desired mask pattern. Finally, the pattern is permanently transferred onto the wafer surface in an etching process wherein, for example, a chemical etchant is used to etch the portions of the wafer surface not protected by resist.